Publications

学术发表

论文按第一作者／通讯作者与合作作者两类分列，每类内部大致按重要性与时间排序。带下划线者为实验室成员。

累计发表论文 50 余篇，其中第一作者 14 篇、通讯作者 17 篇。下表列出代表性论文，每条末尾附出版商 DOI、arXiv 预印本或 Google Scholar 检索链接。

dblpYaoyu Tao 计算机科学文献索引
Google Scholar按作者检索 Yaoyu Tao

一作／通讯论文

包含第一作者、共同第一作者、通讯作者与共同通讯作者论文。共一表示共同第一作者，通讯表示通讯或共同通讯作者。

01 Lei Cai, Yaoyu Tao, Chenchen Xie, Longhao Yan, Shiqian Li, Ruihong Shen, Zelun Pan, Xile Wang, Bowen Wang, Daijing Shi, Yihang Zhu, Teng Zhang, Yixin Zhu, Xi Li, Zhitang Song, Ru Huang, Yuchao Yang. A sub-10-millisecond neural dynamical system based on phase-change memristors. Science, 2026, 393(6806): 105–112. 共一通讯 DOI Google Scholar

02 Lei Cai, Yaoyu Tao, Teng Zhang, Chang Liu, Pek Jun Tiw, Lianfeng Yu, Zelun Pan, Longhao Yan, Haoyang Luo, Yihang Zhu, Bowen Wang, Bonan Yan, Xiyuan Tang, Ru Huang, Yuchao Yang. A first-principle hetero-integrated Fourier transform system based on memristors. Nature Electronics, 2025. 共一通讯 DOI Google Scholar

03 Lianfeng Yu, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Ziang Xie, Yihang Zhu, Bonan Yan, Yaoyu Tao, Yuchao Yang. Fast and reconfigurable sort-in-memory system enabled by memristors. Nature Electronics, 2025, 14: 1076. 通讯 DOI arXiv Google Scholar

04 Jiarong Wang, Keqin Liu, Pek Jun Tiw, Dawei He, Lianfeng Yu, Bowen Wang, Jinxuan Bai, Teng Zhang, Xin Shan, Yang Yang, Yuzhe Wang, Yongsheng Wang, Yaoyu Tao, Xiaoxian Zhang, Yuchao Yang. Homogeneous integration of two-dimensional material-based optoelectronic neurons and ferroelectric synapses for neuromorphic vision. Nature Communications, 2026, 17(1): 1373. 通讯 Google Scholar

05 Chang Liu, Pek Jun Tiw, Teng Zhang, Yanghao Wang, Lei Cai, Rui Yuan, Zelun Pan, Wenshuo Yue, Yaoyu Tao, Yuchao Yang. VO₂ memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things. Nature Communications, 2024, 15: 1523. 通讯 DOI Google Scholar

06 Lianfeng Yu, Teng Zhang, Yang Han, Bowen Wang, Ziang Xie, Haochen Zhang, Jiaxin Liu, Longhao Yan, Pek Jun Tiw, Daijing Shi, Lei Cai, Yaoyu Tao, Yuchao Yang. High-concurrency tri-mode memristor-based ODE solver. Nature Communications, 2025. 通讯 DOI Google Scholar

07 Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang. A configurable successive-cancellation list polar decoder using split-tree architecture. IEEE Journal of Solid-State Circuits (JSSC), 2020, 56(2): 612–623. 第一作者 Google Scholar

08 Yaoyu Tao, Zhengya Zhang. HiMA: A fast and scalable history-based memory access engine for differentiable neural computer. IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021: 845–856. 第一作者 arXiv Google Scholar

09 Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Yaoyu Tao, Yuchao Yang. MeMCISA: Memristor-enabled memory-centric instruction-set architecture for database systems. IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024: 1678–1692. 通讯 Google Scholar

10 Junkang Zhu, Yaoyu Tao, Zhengya Zhang. eNODE: Energy-efficient and low-latency edge inference and training of neural ODEs. IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023: 802–813. 共一 Google Scholar

11 Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang. A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm² configurable successive-cancellation list polar decoder using split-tree architecture in 40nm CMOS. IEEE Symposium on VLSI Circuits, 2019: C240–C241. 第一作者最佳论文奖提名 Google Scholar

12 Zelun Pan, Longhao Yan, Xile Wang, Bowen Wang, Yueying Luo, Zhe Zhan, Xi Li, Yuqi Li, Lei Cai, Teng Zhang, Minghui Yin, Yaoyu Tao, Zhitang Song, Yuchao Yang. A 40nm mixed-precision PCM chip with fused analog/digital compute-in-memory and adaptive drift compensation for embodied AI applications. IEEE International Electron Devices Meeting (IEDM), 2025. 通讯 Google Scholar

13 Yaoyu Tao, Zhengya Zhang. DNC-aided SCL-flip decoding of polar codes. IEEE Global Communications Conference (Globecom), 2021: 1–6. 第一作者最佳论文奖 arXiv Google Scholar

14 Yaoyu Tao, Shuanghong Sun, Zhengya Zhang. Efficient post-processors for improving error-correcting performance of LDPC codes. IEEE Transactions on Circuits and Systems I (TCAS-I), 2019, 66(10): 4032–4043. 第一作者 arXiv Google Scholar

15 Jinxuan Bai, Dawei He, Bingjie Dang, Keqin Liu, Zhen Yang, Jiarong Wang, Xiaoxian Zhang, Yongsheng Wang, Yaoyu Tao, Yuchao Yang. Full van der Waals bipolar ferroelectric configurable optical hetero-synapses for in-sensor computing. Advanced Materials, 2024, 36(50): 2401060. 通讯 Google Scholar

16 Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang. Accelerating neural-ODE inference on FPGAs with two-stage structured pruning and history-based stepsize search. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), 2023: 177–183. 通讯 Google Scholar

17 Yang Han, Lianfeng Yu, Yaoyu Tao, Yuchao Yang. MGPA: A memristor-based genome processing accelerator for single-cell RNA sequencing. Design, Automation and Test in Europe Conference (DATE). 通讯 Google Scholar

18 Lianfeng Yu, Zhaokun Jing, Yuchao Yang, Yaoyu Tao. Fast and scalable memristive in-memory sorting with column-skipping algorithm. IEEE International Symposium on Circuits and Systems (ISCAS), 2022: 590–594. 通讯 arXiv Google Scholar

19 Lei Cai, Lianfeng Yu, Wenshuo Yue, Yihang Zhu, Zhiyu Yang, Yuqi Li, Yaoyu Tao, Yuchao Yang. Integrated memristor network for physiological signal processing. Advanced Electronic Materials, 2023, 9(6): 2300021. 通讯 Google Scholar

20 Zhiyu Yang, Keqin Liu, Rui Yuan, Xulei Wu, Lei Cai, Teng Zhang, Yaoyu Tao, Yufeng Jin, Yuchao Yang. Seizure detection using dynamic memristor-based reservoir computing and leaky integrate-and-fire neuron for post-processing. APL Machine Learning, 2023, 1: 046123. 通讯 Google Scholar

21 Yaoyu Tao, Cedric Choi. High-throughput split-tree architecture for nonbinary SCL polar decoder. IEEE International Symposium on Circuits and Systems (ISCAS), 2022: 2057–2061. 第一作者 arXiv Google Scholar

22 Yaoyu Tao, Qi Wu. An automated FPGA-based framework for rapid prototyping of nonbinary LDPC codes. IEEE International Symposium on Circuits and Systems (ISCAS), 2019. 第一作者 arXiv Google Scholar

23 Yaoyu Tao, Youn Sung Park, Zhengya Zhang. High-throughput architecture and implementation of regular (2, d_c) nonbinary LDPC decoders. IEEE International Symposium on Circuits and Systems (ISCAS), 2012: 2625–2628. 第一作者 Google Scholar

合作论文

与器件、材料、系统等方向团队联合完成的工作。

01 Wenshuo Yue, Teng Zhang, Zhaokun Jing, Kai Wu, Yuxiang Yang, Zhen Yang, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Yibo Lin, Yaoyu Tao, Bonan Yan, Ru Huang, Yuchao Yang. Scalable universal Ising machine enabled by interaction-centric storage and compute-in-memory technology. Nature Electronics, 2024. DOI Google Scholar

02 Wenshuo Yue, Kai Wu, Zhiyuan Li, Juchen Zhou, Zeyu Wang, Teng Zhang, Yuxiang Yang, Lintao Ye, Yongqin Wu, Weihai Bu, Shaozhi Wang, Xiaodong He, Xiaobing Yan, Yaoyu Tao, Bonan Yan, Ru Huang, Yuchao Yang. Physical unclonable in-memory computing for simultaneously protecting private data and deep learning models. Nature Communications, 2025. Google Scholar

03 Youn Sung Park, Yaoyu Tao, Zhengya Zhang. A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. IEEE Journal of Solid-State Circuits (JSSC), 2014, 50(2): 464–475. Google Scholar

04 Youn Sung Park, Yaoyu Tao, Zhengya Zhang. A 1.15 Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. IEEE International Solid-State Circuits Conference (ISSCC), 2013: 422–423. Google Scholar

05 Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang. A 4.68 Gb/s belief propagation polar decoder with bit-splitting register file. IEEE Symposium on VLSI Circuits, 2014: 1–2. Google Scholar

06 Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, et al. Arvon: A heterogeneous system-in-package integrating FPGA and DSP chiplets for versatile workload acceleration. IEEE Journal of Solid-State Circuits (JSSC), 2023. Google Scholar

07 Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, et al. Arvon: A heterogeneous SiP integrating a 14nm FPGA and two 22nm 1.8 TFLOPS/W DSPs with 1.7 Tbps/mm² AIB 2.0 interface. IEEE Symposium on VLSI Circuits, 2023: C7-1. Google Scholar

08 Yihan Fu, Anjunyi Fan, Wenshuo Yue, Hongxiao Zhao, Daijing Shi, Qiuping Wu, Jiayi Li, Xiangyu Zhang, Yaoyu Tao, Yuchao Yang, Bonan Yan. PROCA: Programmable probabilistic processing unit architecture with accept/reject prediction and multicore pipelining for causal inference. IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025. Google Scholar

09 Longhao Yan, Zhe Zhan, Zelun Pan, Bowen Wang, Yaoyu Tao, Yuchao Yang. An 8Mb learning-aware RRAM compute-in-memory accelerator for embodied self-supervised learning. IEEE International Electron Devices Meeting (IEDM), 2025. Google Scholar

10 Longhao Yan, Zitong Zheng, Xi Li, Xile Wang, Zhe Zhan, Jiukai Fang, Minghui Yin, Zelun Pan, Song Jia, Yaoyu Tao, Zhitang Song, Yuchao Yang. Efficient multimodal fusion with intelligent predictive programming based on 64-core PCM compute-in-memory processor. IEEE International Electron Devices Meeting (IEDM), 2025. Google Scholar

11 Longhao Yan, Yuqi Li, Xi Li, Zelun Pan, Zeyu Wang, Xile Wang, Bowen Wang, Zhe Zhan, Xiyuan Tang, Yaoyu Tao, Woo-Ping Ge, Zhitang Song, Yuchao Yang, Ru Huang. Neural manifold learning based on 40nm dual-mode PCM compute-in-memory chip with hardware adaptive drift compensation. IEEE International Electron Devices Meeting (IEDM), 2024. Google Scholar

12 Zhen Yang, Wenshuo Yue, Chang Liu, Yaoyu Tao, Pek Jun Tiw, Longhao Yan, Yuxiang Yang, Teng Zhang, Bingjie Dang, Keqin Liu, Xiaodong He, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Ru Huang, Yuchao Yang. Fully hardware memristive neuromorphic computing enabled by the integration of trainable dendritic neurons and high-density RRAM chip. Advanced Functional Materials, 2024: 2405618. Google Scholar

13 Longhao Yan, Qingyu Wu, Xi Li, Chenchen Xie, Xilin Zhou, Yuqi Li, Daijing Shi, Lianfeng Yu, Teng Zhang, Yaoyu Tao, Bonan Yan, Min Zhong, Zhitang Song, Yuchao Yang, Ru Huang. Neural architecture search with in-memory multiply–accumulate and in-memory rank based on coating layer optimized C-doped Ge₂Sb₂Te₅ phase change memory. Advanced Functional Materials, 2023: 2300458. Google Scholar

14 Chenchen Xie, Yuqi Li, Longhao Yan, Sannian Song, Houpeng Chen, Ruijuan Qi, Xi Li, Yihang Zhu, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Gaoming Feng, Yuchao Yang, Zhitang Song. Memristive in-memory object detection with 128Mb C-doped Ge₂Sb₂Te₅ PCM chip. Advanced Science, 2025: e05678. Google Scholar

15 Yanghao Wang, Pek Jun Tiw, Yuheng Liu, Yaoyu Tao, Teng Zhang, Yuchao Yang. Local active memristive oscillator enables controllable complex behaviors and frequency domain extraction. National Science Review (NSR), 2025. Google Scholar

16 Yingming Lu, Zhen Yang, Yaoyu Tao, Lei Cai, Teng Zhang, Longhao Yan, Ru Huang, Yuchao Yang. Energy-efficient online training with in situ parallel computing on electrochemical memory arrays. Advanced Intelligent Systems, 2025: 2401068. Google Scholar

17 Tengyu Zhang, Tong Xie, Haoyang Luo, Yixuan Hu, Yaoyu Tao, Xiyuan Tang, Yuan Wang, Runsheng Wang, Meng Li. A 28nm 534.6 TOPS/W mixed-precision edge accelerator for embodied AI using stochastic computing. IEEE Asian Solid-State Circuits Conference (A-SSCC), 2025. Google Scholar

18 Yanghao Wang, Pek Jun Tiw, Yaoyu Tao, Teng Zhang, Yuchao Yang. Harnessing Turing instability through VO₂-based negative feedback loop coupling system. IEEE European Solid-State Electronics Research Conference (ESSERC), 2025. Google Scholar

19 Xile Wang, Longhao Yan, Xi Li, Yaoyu Tao, Zhitang Song, Yuchao Yang. An efficient pipeline programming scheme based on 40nm PCM compute-in-memory chip for CNNs. IEEE Electron Devices Technology and Manufacturing (EDTM), 2025. Google Scholar

20 Quan Zhang, Longhao Yan, Yaoyu Tao, Ru Huang, Yuchao Yang. On-chip write and verify and endurance enhancer circuits towards multi-level RRAM array. IEEE Electron Devices Technology and Manufacturing (EDTM), 2024: 1–3. Google Scholar

21 Wenshuo Yue, Zhaokun Jing, Bonan Yan, Yaoyu Tao, Teng Zhang, Ru Huang, Yuchao Yang. Multifunctional RRAM chip with configurability for sparsity-aware in-memory Ising machine. IEEE Conference of Science and Technology for Integrated Circuits (CSTIC), 2024. Google Scholar

22 Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang. Efficient in situ error detection enabling diverse path coverage. IEEE International Symposium on Circuits and Systems (ISCAS), 2013: 773–776. 最佳论文奖提名 Google Scholar

学术影响

研究成果被多位领域内学者引用并评价，相关电路设计亦被科技企业在其商用专利中引用。

学者	评价与引用
Muriel Médard（美国工程院院士，MIT 教授）	引用并评价为极化码芯片的代表性工作
Erdal Arıkan（极化码发明人，香农奖得主，IEEE Fellow）	引用为极化码芯片的代表性工作
Naresh Shanbhag（美国半导体创新奖得主，UIUC Jack Kilby 讲席教授，IEEE Fellow）	评价为极化码芯片的代表性工作
尤肖虎（中国科学院院士）	引用为低密度奇偶校验芯片、以及人工智能辅助通信编解码芯片的代表性成果
Francis Chi Moon Lau（香港大学教授，IEEE 千禧年奖章得主）	引用为编解码算法与电路协同设计的代表性工作
Hideki Ochiai（日本大阪大学教授，IEEE Fellow）	引用为人工智能与通信结合的代表性工作
Yeong-Luh Ueng（吴大猷纪念奖得主，台湾清华大学教授）	评价成果显著降低了数据通信的能耗
Andreas Peter Burg（EPFL 教授，IEEE TVLSI/TSP 主编）	引用为连续取消列表算法芯片的代表性工作
Warren Gross（麦吉尔大学电子与计算机工程系主任）	引用为信号处理领域的代表性芯片

此外，相关电路设计受到华为技术有限公司、美国高通公司、韩国 SK 海力士公司等企业在其商用专利中引用。